1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory device. More particularly, the present invention is directed to a method of manufacturing a twin-ONO-type SONOS memory device, which can function as a 2-bit operating memory device with asymmetric programming, using a reverse self-alignment process.
2. Description of the Related Art
In recent years, nonvolatile semiconductor memory devices have been used in various applications. Nonvolatile semiconductor memory devices can not only electrically erase and program data but also retain data even during interruption of power supply. An example of a nonvolatile semiconductor memory device is a flash memory cell.
Conventionally, stack-gate-type flash memories, in which floating gates and control gates are stacked, have been developed and produced in mass. Floating gates are intended for programming charges, and control gates are intended for controlling the floating gates.
As capacitances of memory devices become larger and the number of gate arrays required for forming complicated circuits increases, techniques of forming fine patterns with a sub-0.10-μm linewidth become indispensable. Although conventional stack-gate-type nonvolatile memory cells have been constantly scaled down, photolithographic and etching processes for forming hyperfine devices are about to reach the technical limits. That is, in addition to scaling vows, patterning a structure in which a floating gate and a control gate are stacked becomes complicated due to a high step difference or a high aspect ratio.
On the other hand, research on SONOS (or MONOS) nonvolatile cells with trapped charges has also progressed to develop single-gate structures such as MOSFETs.
FIG. 1 illustrates a schematic cross-sectional view of a typical SONOS memory cell.
Referring to FIG. 1, to form a SONOS (or MONOS) cell, a source and a drain 15 are formed in a semiconductor substrate 10, such as a p-Si substrate, and then an oxide-nitride-oxide (ONO) dielectric layer 20 and a gate 30 are sequentially formed on the semiconductor substrate 10. The SONOS cell uses the ONO dielectric layer 20 in place of a gate oxide layer of a transistor. In the SONOS cell, a floating gate for programming charges is replaced by the ONO dielectric layer 20. Thus, electrons or holes are injected into a silicon nitride layer 23 sandwiched between thin silicon oxide layers 21 and 25 included in the ONO dielectric layer 20.
Since the ONO dielectric layer 20 is about 10 to 20 nm thick, the step difference is not very much. Therefore, scaling down the SONOS cell within a permitted photolithographic limit is relatively easy. Also, a number of additional processes related to the floating gates can be omitted, thus simplifying the entire manufacturing process.
Meanwhile, for several years, some manufacturers have adopted SONOS memories for obtaining highly integrated nonvolatile memory devices. These manufacturers proposed and attempted to manufacture 2-bit SONOS memories that use asymmetric programming without floating gates.
FIG. 2 is a schematic diagram illustrating the operations of a typical 2-bit memory device when a voltage VDS is applied from a drain to a source in the memory device.
Referring to FIG. 2, a 2-bit memory technique enables the 2-bit memory device to be twice as much integrated as a conventional stack-gate-type flash device having the same area. A 2-bit memory operation comprises: (i) forwardly injecting electrons into a portion of a silicon nitride layer 23 positioned at an edge of a gate 30 by applying a high voltage to a control gate 30 and one of source and drain junctions 15 of a transistor, i.e., by using channel hot electron injection (CHEI), and (ii) reversely reading data by applying a voltage to the gate 30 and the other source and drain.
An erasing operation comprises applying a high voltage to a drain junction 15 and grounding the gate 30 and a substrate 10 bulk. Thus, the programmed electrons in the silicon nitride layer 23 are combined with holes using band-to-band tunneling (BtBT) in an overlap region between the gate 30 and a junction 15.
In an asymmetric charge trap operation, when the linewidth of the gate is relatively high, a spatial interval between programmed traps is sufficient enough that no serious problem occurs in the 2-bit operation. However, as the linewidth of the gate 30 is reduced to about 0.10 μm or less, the 2-bit memory characteristics may be degraded. This is because the charges trapped in the ONO dielectric layer 20 by the CHEI have a certain degree of dispersion, which increases with operation time.
Inset of FIG. 3A illustrates a spatial distribution graph of charges in a typical SONOS, the charges being injected into the silicon nitride layer 23 after memory programming. Variation of drain current with gate voltage in a fresh cell and in an already programmed cell is illustrated in FIG. 3A. FIG. 3B illustrates a retention characteristic of a typical SONOS, which results from a redistribution of injected charges with operation time (t).
In a typical SONOS, in programming by CHEI, charges are injected into the silicon nitride layer. The distribution graph of the charges is obtained using a simulation model as shown in FIG. 3A. That is, charge distribution in each of a fresh cell and a programmed cell is obtained by simulation fitting. Referring to FIG. 3B, since the injected charges are redistributed in time (t), the charge retention characteristic is degraded. The decay rate N(t) of a distribution center can be expressed by the equation shown in FIG. 3B. Referring to FIG. 3B, as time t tends to t′, the height of the distribution graph decreases, raising the degree of dispersion.
If, in a SONOS, charges are scattered after programming and charges programmed in a central channel region are not completely erased in repetition of programming and erasing, residual charges may be accumulated on the channel region. The accumulated charges may deteriorate the SONOS endurance. Similarly, after hole charges are programmed, accumulated holes may make the endurance of the device poor.
FIGS. 4A and 4B are graphs illustrating the endurance of a typical SONOS. Variation of cell threshold voltage with number of programming and erasing cycles is illustrated in FIGS. 4A and 4B.
In FIG. 4A, initially, a substrate bulk and a source of a SONOS cell are grounded. After programming and erasing are repeated, the endurance curve is obtained as shown in FIG. 4A. Here, the programming is performed by applying 11 V and 6 V to a gate and a drain, respectively, for 100 μs, and the erasing is performed by applying 0V, 10V, 10V, and 0V to the gate, the drain, the source, and the substrate bulk, respectively, for 100 μs. Reference numeral 41 denotes a case where the cell is turned on, while reference numeral 45 denotes a case where the cell is turned off.
In FIG. 4B, only erasing conditions are changed from the case of FIG. 4A. That is, erasing is performed by applying 0V, 10V, 4V, and 0V to a gate, a drain, a source, and a substrate bulk, respectively. Here, an electric field is formed between the source and the drain so that holes formed by band-to-band tunneling (BtBT) can be efficiently injected into a central channel region. Reference numeral 43 denotes a case where a cell is turned on, while reference numeral 47 denotes a case where the cell is turned off.
Based on the results, it can be inferred that a tail of electron dispersion exists in the central channel region at a certain level. Although there is a possibility that the distribution of electrons or holes in an ONO dielectric layer can be minimally adjusted by optimization of process conditions or by appropriate control of driving voltage, shorter and shorter gate lengths cannot assure the 2-bit characteristics anymore.